The invention relates to computer system memory architectures and, more particularly, to the control of memory access operations based on a memory page cache configured to provide a programmable number of open pages.
Many current computer system memory architectures use synchronous random access memories (synchronous RAM) such as synchronous dynamic random access memory (SDRAM), SyncLink dynamic random access memory (SLDRAM), and Rambus dynamic random access memory (RDRAM). The SyncLink standard has been assigned the tentative designation of IEEE-1596.7 by the Microprocessor and Microcomputer Standards Committee (MMSC) of the Institute of Electrical and Electronics Engineers (IEEE). The Rambus(copyright) standard is published by Rambus, Incorporated of Mountain View, Calif.
In addition to providing inherently faster operation than previous types of memories, synchronous RAM may generally be organized into banks. Banks represent a physical compartmentalization of memory space, where each bank may correspond to a unit or array of physical memory. A bank may be further divided into pages, where a page is typically defined in terms of a row address. All those memory locations in a bank having a common row address are said to be on the same page of memory.
One feature of banked memory systems is that consecutive memory access operations to a common page may be performed faster than consecutive memory access operations directed to different pages within the same bank. As shown in FIG. 1, the time to perform first access 100 (directed to a first page in a first bank) includes the time needed to select the target page 102 and the time to select the uniquely targeted memory location 104. If second access 106 is directed to another memory location in the same page, the time required to complete the memory transfer includes that needed to select the target location 108; no time is required for page selection. If a subsequent, third access 110 is directed to a different page in the same bank however, the previously selected (open) page must be closed (an operation referred to as precharging 112) before access 110 may proceed. Following precharge operation 112, access 110 continues through page selection 114 and data selection 116 phases. Because precharge operations require some time to complete, they generally limit the speed with which a sequence of memory access operations may be performed.
As indicated above, by leaving a page open after completing a memory access operation the precharge time penalty may be avoided when a subsequent bank access is directed to that same page (a page hit). Conversely, when a subsequent bank access is to a different page (a page miss), the open page must be closed and the precharge operation performed before the memory access operation may proceed. Thus, while there exists benefits to leaving a page open in the event there are frequent page hits, there also exists time penalties associated with a large number of page misses when pages are kept/left open.
As the number of banks in a memory system increases, the potential for improved memory access bandwidth increases. The potential improvement may generally be attributed to two factors: (1) the ability to avoid precharge when making successive accesses to a common page of memory; and (2) the ability to hide precharge by interleaving memory accesses between different banks. Actual improvement in memory system performance, however, may be less than expected. For example, as the number of memory banks increase so does the amount of hardware needed to track each open page. Thus, the hardware overhead associated with maintaining a large number of pages in the open state may set a practical upper limit on the number of pages that may be simultaneously open. Further, some applications and devices are known to exhibit low degrees of memory access localityxe2x80x94memory access operations by these types of entities do not generally benefit, and may actually slow overall access operations due to frequent page misses. Thus, there is a need for memory systems having improved performance.
In one embodiment, the invention provides a computer system comprising a memory (having a plurality of pages), a memory controller adapted to maintain a programmable number of the plurality of pages in an open state at one time, and a page limit value (representing the programmable number of pages that can be kept open at one time) accessible to the memory controller. The page limit value may be a user specified value, a function of the total number of banks in the memory, a function of the type of processing performed by the computer system, or it may periodically change during the course of system operations.